DVCon gears up for March in San Jose

By Chris Edwards |  No Comments  |  Posted: January 12, 2024
Topics/Categories: Blog - EDA  |  Tags: , , ,

Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 Design and Verification Conference and Exhibition United States (DVCon US).

To be held March 4-7 at the DoubleTree by Hilton Hotel in San Jose, California, DVCon will feature a two-day series of technical sessions bracketed by two days of tutorials and workshops.

“Now in its 36th year, DVCon offers attendees presentations addressing day-to-day challenges, real experiences, and solutions, as well as a peek into what’s on the horizon. DVCon also provides many networking opportunities during the exhibition and coffee breaks to give participants time to engage with colleagues and experts in the industry to learn about new technologies and standards,” said Tom Fitzpatrick, DVCon US 2024 general chair.

The technical sessions will feature 42 paper presentations on subjects from coverage, formal and mixed-signal design and verification to verification planning and regression management and SystemVerilog verification techniques.

The conference will have two keynotes, the first given by Paul Cunningham, Cadence Design Systems senior vice president, and a second by AMD corporate fellow Alex Starr. “These sessions are included in the free exhibits-only registration package, so I hope everyone will attend,” Fitzpatrick added.

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