DAC2012: Can FD-SOI shrink chips, solve FinFET issue for SoCs?

By Luke Collins |  1 Comment  |  Posted: June 4, 2012
Topics/Categories: Commentary, Conferences  |  Tags: , ,

What are the chances that FD SOI (Guide) will become a mainstream process for future nodes?

The arguments against include the limited supply chain for the wafers so far, and the industry’s general discomfort with carrying the costs of developing DOI further as a hedge against potential difficulties with FinFETs.

Steve Longoria, senior vice present of strategic world-wide business development for wafer makers Soitec, said: “The industry likes to stay where it is comfortable and has been doing a fantastic job of scaling bulk CMOS. I think that is why partially depleted SOI did not take off beyond its use in microprocessors by AMD and Intel.

“What’s very different now is that bulk CMOS is coming to its end of life. There is this thing called finFETs (Guide) and outside of Intel, no one knows how to build that for SoCs with multiple threshold voltages,” claims Longoria.

“Planar FD-SOI is a fantastic solution for 28nm  because it enables the industry to keep on keeping on at the design level. We think we can stay with planar transistors for 20nm and our data suggests it  could do 14nm as well.

“We don’t think that there will be many customers for planar bulk CMOS at 20nm. Physical design kits come in and out of the market and continue to be very unattractive in terms of the lack of power/performance advantage and the cost premium over 28nm.”

Some analysts are predicting that the cost per gate will increase with the shift from 28nm to 20nm processes.

“It’s that dynamic that is going to drive change in our industry.”

Manufacturing cost

Longoria argues that building devices on FD-SOI need not be more expensive than working on bulk: he says that although SOI wafers are about $500 each, compared with bulk wafers at $120 to $150, defining the transistor channel as a wafer-level epitaxial growth process rather than in a series of advanced lithography steps, saves processing cost.

Performance benefits are said to include good channel control, thanks to the option to use back biasing, better DIBL and fewer effects from random dopant variations. The result, Longoria says, is much better control of channel leakage and the opportunity to push device performance.

Area and yield

The reduced impact of dopant variability also enables designers to make structures such as SRAM cells smaller  because they no longer need the headroom to cope with the variability. This also gives a yield advantage.

Consultant Handel Jones of IBS is preparing a white paper on the advantages of SOI for Soitec.

According to Longoria, in early results “we’re seeing around a 15 to 18% increase in die per wafer for a typical SoC built on FD-SOI as compared to on an HKMG bulk process.”

In terms of performance, Soitec is quoting the ability to up the clock rate of a Cortex A9 core at the same operating voltage from 1.5GHz to 2.2GHz by shifting it from a 28nm low-power bulk CMOS process to 28nm FD SOI.

Model availability

According to Longoria, ST Microelectronics has models for a 28nm FD-SOI process that is going into production.

“That environment will be made available to customers by a partner foundry to ST,” he said.

“At 20nm we have silicon validated models that have been developed by the IBM Alliance and are openly distributed through the SOI Consortium.”

FinFETs on SOI?

One of the issues with FinFETs at the moment is that it is not clear how easy it will be to adjust their characteristics to achieve the variety of properties, such as high-performance transistors or  low-leakage transistors, that you might need to build an SoC. Longoria says that ‘3D FD-SOI’ may be the way before, and he is not the only one who thinks so.

“We are working with IBM and other who see FinFETs on oxide as the way to go for SoCs,” he said.

“What makes FD-SOI attractive is that the channel is produced at wafer level,” he said. “If we put a  little thicker buried oxide layer under the silicon and make the top silicon 30nm thick then we can also fix the fin height at wafer level, using the buried oxide to simplify manufacturing by acting as an etch stop.”

“Managing the fin to fin variability will be critical to getting a high yield of FInFET devices.”

One Response to DAC2012: Can FD-SOI shrink chips, solve FinFET issue for SoCs?

  1. Pingback: Doping gives finFETs threshold control | Tech Design Forums

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors