One argument that proponents of fully depleted silicon-on-insulator (FD-SOI) are using against the widespread use of finFETs lies in the problem of adjusting threshold voltage (Vt) on the vertical devices.
“To achieve SoC devices you can’t have a device with only one Vt,” said Chung-Hsun Lin of IBM Research, New York at the VLSI Technology Symposium on Tuesday. IBM has been working with a team from GlobalFoundries to see if there is a way to get devices with different Vt settings easily into an SoC.
At first sight, the finFET is not a cooperative structure for SoC users. You cannot readily use back-biasing to control the threshold and, as the finFET was conceived to use an undoped channel – relying purely on dimensions to maintain gate control – channel doping appears to be out of the question. The most obvious approach is to control the work-function of the gate but “that increases process complexity” said Lin.
Other possibilities are fin thickness and channel length, said Lin, but these tend to reduce logic. Although it seems a retrograde step, channel doping is an option. IBM and GlobalFoundries decided to look at whether it is a realistic option.
“Because this is a conventional approach from the planar-device era, we know how to do it. It’s a relatively simple process compared to workfunction tuning. And it’s not constrained by gate pitch,” said Lin. “There are, however, disadvantages. You get lower mobility and you also pay a penalty in terms of variability from random dopant fluctuations.”
The IBM and GlobalFoundries ran SRAM test wafers using representative 20nm and 22nm devices to see how bad the situation could get with doped channels. The results so far suggest that the performance hit is not too bad, particularly when it comes to the impact on overall variability as long as the doping concentration is kept reasonably low.
Process engineers will have to pay attention to how they select the base device as counterdoping with arsenic results in significantly worsened performance, particularly on the Ion/Ioff metric – which would be problematic for high-performance or low-power devices – according to the tests. In general, it seems you want to use channel doping to increase Vt rather than cut it.
Using boron doping to provide the Vt shift, the fall in mobility for a 150mV change worked out to be a hit of 10 per cent on the drive current. Work on long-channel devices suggested a much higher hit due to stronger Coulombic scattering. Also, the buildup of a body charge strengthened the vertical field – both bad for mobility overall. However, the carriers move from the body of the fin to the walls as field increases, which changes the nature of the scattering. The result was that, under high field conditions, surface scattering predominates, so the mobility degradation is not as bad as might be expected at least with high overdrive.
At first, the experiments showed that channel doping had the reverse effect on DIBL to the case on planar devices. However, Lin argued that the initial calculations, based on a constant-current model, did not take into account the special characteristics of a thin device such as a finFET. Once the model was adjusted, DIBL behavior returned to normal, backed up by refined simulations on mobility.
Variability does not rule out the use of channel doping in finFETs for SoC usage, according to the work. “It does degrade but compared to conventional planar devices it’s still much better you can control your channel doping to be less than 2 x 1018cm-3.”
At a doping concentration of 6×1017cm-3, about a third of the variability came from random dopant fluctuations with the majority still due to the combination of variations in fin height, gate length and workfunction.