The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard that will include support for an extended version of the DRC+ technology donated last year by GlobalFoundries and bring more automated intelligence into the way rules are used and maintained as processes and IC designs evolve. In effect it will allow manufacturers to build their own yield search engine.
DRC+ brings the concept of pattern matching to pre-manufacturing design-rule checks and, potentially, a more streamlined way of defining design rules that can prevent the explosion of prohibited structures in sub-30nm designs.
Luigi Capodieci, director of design for manufacture and CAD at GlobalFoundries, explained during a session organised by Si2 said a driver for the technique supported by DRC+ is the growing regularization of design at the physical level.
“Intel has shown that the regularisation and strong co-optimization of design and technology is practical but also fundamental to breaking through the limits on more Moore and more than Moore,” said Capodieci.
These regular structures mean that instead of looking for design features that are against the rules, it begins to make sense to treat everything as forbidden unless specifically allowed by the DRC database. So the emphasis shifts from proscription to prescription of known good patterns.
The design rules themselves are driven increasingly by proximity effects – such as the tip of a line influencing the width of the line that passes nearby. And these effects tend to be consistent. Others will produce less undesirable effects.
“Many of the geometrical configurations used are similar. So why not collect them together and create a library of yield attractors?” Capodieci said. “You can classify features by printability.”
Capodieci added: “This doesn’t come in isolation. You need to work on the ecosystem. Designers have to know about the good patterns. The router needs to know about the patterns: it’s better to do this during implementation rather than sign-off.”
Capodieci argued that this kind of attention to DRC will be mandatory for 20nm and the double patterning lithography that it will rely on as some common patterns used today will not split cleanly between masks and cause yield problems if they are stitched.
“We will provide tools to make double patterning viable,” he said. “One tool is a scoring module and the other is a DRC+ library for double patterning. Later on we will provide good patterns that are easily decomposable into two masks.”
With DRC+, GlobalFoundries is building an active library of design features and their impact on yield. Capodieci referred to the idea as a ‘Google check’: a searchable index of all the patterns that appear on designs that come into the fab. “We build a library of patterns that are not necessarily bad but which are associated with certain manufacturing conditions. We pass that data to the manufacturing floor so they know the patterns that have been seen. They can use those to zoom in when performing failure analysis and see the yield attractors that have already been analysed. The library of yield attractors has become a knowledge base.”
This search-engine technique is something that Jake Buurma, vice president of west coast operations at Si2 sees being adopted more widely and is one of the thrusts of the DRC+ standardization work.
“For DRC+, it’s time has come – we can use the same technology that Google uses to look a millions of layout configurations.”
Preparing for a demonstration at DAC on Monday, the working group has taken the DRC+ donation from GlobalFoundries and added elements to make it more widely applicable.
“We need to have user libraries on top of the foundry libraries,” said Buurma. “Now we are not talking about one library from a foundry but using multiple libraries at once, maybe from IP providers or from your mixed-signal experts.
“There are end users doing mixed-signal work who want to find yield attracting patterns,” said Buurma.
The result is a unified layer model that adds additional tags to the core XML definition to allow multiple libraries to coexist as well as the ability to define multiple levels of tolerance. “We need fuzziness around the patterns, so we have added tolerances,” said Buurma.
A further addition is tagging for chip-level features. For example, if a feature on the ‘polysilicon’ layer is known to be a gate, this can be handled differently from interconnect. “If you know that a gate is a gate, there may be different tolerances you want to use to something that you know is not a gate. And we can tell the manufacturing people where to look: they look for the critical areas rather than looking across the whole chip,” Buurma explained.
“Our top task is the unified layer model,” said Buurma. “We need it for the OpenPDK and OpenDFM. OpenDFM will convert the DRC+ rules for the tools.”
The demonstration was designed to take a DRC+ rule desk and provide rules for three different DRC tools from Cadence Design Systems, Mentor Graphics and Synopsys. The data model also works with a variety of scripting languages. “We want to build standards on the data model not a language or format. With the right data model, it will support different run sets, input formats and tools.”