DAC 2013

May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
May 14, 2013

Jasper adds low-power App to formal family

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
May 14, 2013

Forte Cynthesizer aims at performance, power and ease of use

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.
Article  |  Topics: Blog - EDA, - ESL/SystemC  |  Tags: , , ,   |  Organizations:
May 14, 2013

DAC 2013 REMINDER: ‘No Free Monday’

But you can still get in for free by registering for the 'I Love DAC' scheme by this Friday (May 17th).
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May 14, 2013

DAC 2013 Preview VI: CEO ‘visions’ added

Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.
May 7, 2013

DAC 2013 Preview V: Rounding out the keynotes

Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.
April 29, 2013

DAC 2013 Preview IV: Management and Training Days

DAC 2013 will offer a series of dedicated training courses in SystemVerilog, SystemC, and ARM-based design as well as its regular management day bridging the gap between technology and business.
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April 24, 2013

DAC 2013 Preview III: Embedded

DAC 2013 wants to bridge the gap between hardware and embedded software technical conferences, and has dedicated 35% of this year's technical program to that goal.
Article  |  Topics: Conferences, Blog - EDA, Embedded  |  Tags: , , , , , ,
April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
Article  |  Topics: Blog Topics, Design to Silicon, Verification  |  Tags: , , , , ,   |  Organizations:
April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.

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