DAC 2013 Preview III: Embedded

By Paul Dempsey |  No Comments  |  Posted: April 24, 2013
Topics/Categories: Conferences, Blog - EDA, Embedded  |  Tags: , , , , , ,

The Embedded Systems and Software strand at DAC 2013 accounts for more than 35% of the overall technical program. And so it should. The methodological collision between the software and the hardware worlds needs to become an alignment.

Most projects still start with some kind of hardware design (or at least architectural definition), and software engineers then wait for, perhaps, an early-stage virtual prototype but more typically something relatively close to the final RTL. We’re getting nearer to processes that we can genuinely call hardware-software co-design. But few would claim we’re there yet.

Certainly, the hardware community that has been DAC’s mainstay for exactly 50 years is aware of that. If only because they’ve seen their counterparts in software development come to outnumber them as we’ve moved into the era of the system-on-chip and more recently multicore designs. In itself, programming to exploit the full potential of multicore remains a pressing issue that has driven various initiatives aimed at promoting best practices – and it’s worth noting here that as the market extracts benefit from them, many of these projects got their first major public airings at DACs past.

But what is the meat in the DAC 2013 program to persuade a code-slinger to join the Rubylith brigade – some old stereotypes do die hard?

We’ve picked out a few DAC 2013 sessions across the technical conference that illustrate its bid to achieve some necessary outreach.

Monday June 3

Why programming many-core is not ‘Mission Impossible’
11:00 AM—1:00 PMTutorial, Room 16AB

A team from Austin-based Coherent Logix will show algorithm developers how a many-core processor can be programmed using C and the industry standard Message Passing Interface. A DSP processor based on HyperX technology will be used as the first demonstration vehicle and they’ll further discuss a full LTE PHY and an H.264 encoder. An interactive Eclipse-based environment will be used for development and running the resulting programs on a cycle-accurate instruction set simulator and target hardware.

Supercharge your GPU: Developing and optimizing OpenGL applications using a native IDE across virtual and physical targets
11:00AM-1:00PM, Tutorial, Room 15

Tech Design Forum‘s coverage of OpenGL has generated a lot of interest given its potential application in mobile, automotive and gaming systems, to name but three. This Mentor Graphics-led tutorial looks at the fast-emerging 3D graphics API through the evolution of an embedded system application development and execution flow. The flow is driven with a unified native software IDE with embedded hardware visibility and profiling features, and addresses software-driven debug and optimization from the virtual prototype stage through software rendering implementation to graphics processor environments running on emulators and FPGA-based prototyping boards.

Tuesday June 4

Teaching the old back-end compiler dog new tricks
1:30 PM-3:00PM, Conference, 11AB

Reliability and energy-efficiency requirements are leading demands for new optimization techniques in fields such as instruction-level parallelism and also both reliability- and resource-aware code mappings. Researchers from universities in China, Germany and the US describe what they are doing to address these pressures.

Wednesday June 5

Captcha the Chip!
1:30 PM-3:00PM, Conference, Room 11AB

Where and how can we protect increasingly trust-based and other critical embedded systems from malware attacks? It’s one of the fastest growing concerns that bridges the hardware and software domains. This DAC 2013 session will see various researchers discuss defenses that can be applied at, for example, the power grid, processor architecture and compiled code levels.

Thursday June 6

Embedded: When applications and architectures collide
9:00AM-10:30 AM, Conference, Room 13AB

This is kinda where we came in. Still the purpose of this DAC 2013 session is to highlight first-class designs that balance the eternal demands of power, performance and area. Specific targets for the work included state-of-the-art cryptography, wireless communications, biologically-inspired recognition systems, and ultra low power image processing.

Don’t forget to also read our other DAC 2013 previews:

DAC 2013 Preview I: Putting users first and marking 50 years

DAC 2013 Preview II: Panels

DAC 2013 Preview IV: Management and Training Days

DAC 2013 Preview V: Rounding out the keynotes

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