Blog Topics

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.

Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.

A one-day conference on using agile development techniques for embedded systems takes place in the UK on 3 May.

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.

L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.

Solido aims to bring the types of machine-learning techniques the company has used for its physical-analysis tools to a wider range of EDA tools through the launch of its ML Labs initiative.

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.

For the ninth year, I Love DAC badges will provide free access to the Design Automation Conference exhibition and pavilion sessions.