Blog Topics

DAC's traditional training day is expanding into the field of machine learning this year in Austin.

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.

Engineering consultancy pays undisclosed sum for IMGworks division.

The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.

Can embedded projects that call for both custom hardware and software be agile? It's a question that a conference in early May organized by UK training company Feabhas sought to answer.