Blog Topics

June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
June 1, 2017

DAC 2017 preview: Mentor

Mentor, a Siemens business, has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
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May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
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May 30, 2017

How Mentor realized concurrent engineering for PCB design

The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.
May 29, 2017

ARM extends top end of Cortex-A family

A year on from the last Computex and the launch of the Cortex-A73 and Mali-G71, ARM has launched a new trio of processors aimed not just at smartphones this time but servers and driver-assistance systems.
May 24, 2017

Austemper tools straddle the functional-safety flow

Austemper Design Systems has launched a portfolio of tools that span the development lifecycle of projects that need to demonstrate functional safety.
May 19, 2017

DAC to train on machine learning

DAC's traditional training day is expanding into the field of machine learning this year in Austin.
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May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
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May 17, 2017

Matlab links up with Virtuoso for circuit analytics

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.
May 16, 2017

Cadence adapts Jasper tools for CDC and lint

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
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