IP

September 18, 2019

Ceva shares weights for lower DNN overhead

Ceva has employed a more extensive form of weight compression in its latest generation of DNN processor cores.
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September 18, 2019

Synopsys claims 35TOPS performance from new family of embedded vision cores

IP core focuses on avodiing memory access bottlenecks during processing of complex machine-learning and artificial-intelligence algortihms.
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September 10, 2019

Digital twin points the way to system-level vehicle safety

The digital-twin concept provides several avenues to achieving better safety analysis and is likely to benefit from Siemens' integration of Mentor activities.
September 5, 2019

DVCon keynotes to look at edge computing and network evolution

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
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September 4, 2019

Future memories not so future any more

Non-volatile alternatives to flash are finally moving out of the lab as Applied Materials launches production tools and Arm starts pushing MRAM.
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August 27, 2019

GlobalFoundries takes aim at TSMC’s customers in patent action

GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
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July 27, 2019

A repeatable methodology for modern reset domain crossing issues

Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
July 16, 2019

Arm opts for more flexibility in licensing

Arm has introduced a licensing model that makes it easier to try out cores during a design before committing to production.
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July 5, 2019
ES Design West logo

The road to ES Design West: Design Pavilion

ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
June 18, 2019

RISC-V firms aim for lower-cost design starts

Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
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