IP

July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
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July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
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July 14, 2021

Accellera approves IP security-documentation standard

Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
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June 9, 2021

Xilinx retools Versal for high-end edge AI

Xilinx has reworked its Versal FPGA for edge-AI applications.
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June 3, 2021

Three libraries tune speed and density on TSMC’s 3nm process

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
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May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
May 26, 2021

Arm rolls clickthrough license scheme into Flexible Access

Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
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May 20, 2021

Denser DRAM looks to flash for inspiration

Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
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April 20, 2021

Edge AI focuses on power efficiency at Linley Spring

The Linley Spring Conference saw several vendors present architectures that they claim can deliver more performance to edge systems than what are now traditional approaches.
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April 15, 2021

Portable stimulus moves to version 2.0

The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
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