IP

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.

Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.

Xilinx has reworked its Versal FPGA for edge-AI applications.

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.

Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.

Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.

The Linley Spring Conference saw several vendors present architectures that they claim can deliver more performance to edge systems than what are now traditional approaches.

The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.