A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
The 69th annual IEEE IEDM has issued a call for papers seeking the world’s best original work in all areas of microelectronics research and development.
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
X-Fab Silicon Foundries claims to be the first with a foundry offering for 110nm BCD-on-SOI technology, aimed primarily at automotive designers.
Partners in the UK’s CryoCMOS Consortium have developed models that are expected to help deliver CMOS chips that will work inside cryostats.
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
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