Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.
DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
Arm has put together a program based on its existing Flexible Access model that is intended to provide early-state startups with a broader list of cores they can prototype before needing to take out a full licence.
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
SureCore has started running 30-day trials of its low-power memory compiler.
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