IP

Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.

Ferroelectric memory may be able to stage a comeback thanks to materials innovations as work presented at VLSI Symposium have shown, though there is still plenty to do.

Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.

A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.

The 69th annual IEEE IEDM has issued a call for papers seeking the world’s best original work in all areas of microelectronics research and development.

Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.

X-Fab Silicon Foundries claims to be the first with a foundry offering for 110nm BCD-on-SOI technology, aimed primarily at automotive designers.