The launch of an RC oscillator IP core at the 59th DAC marks a point in Agile Analog’s development where it focuses exclusively on the use of its inhouse Composa tool to create easily retargetable IP as well as being the first in a line of modular building blocks for mixed-signal chips.
Barry Paterson, who recently joined Agile as CEO from Renesas subsidiary Dialog Semiconductor, said the aim of the IP cores was to support mixed-signal teams with basic building blocks that they can combine with their own differentiating circuits as well as other basic blocks that will be added over time as they move through the creation process in Composa.
Paterson claimed the automated approach developed by the company makes it possible to retarget the IP to significantly different process nodes, citing the example of a bandgap that can be ported to 28nm planar and to 12nm finleT processes. Where constraints such as area are particularly important, the company will tune the tool’s output to promote that as a constraint versus power or performance. The company argues its approach generates IP that is equivalent to silicon-proven without having to take each core to each individual process exhaustively.
“Everything is coming through Composa now. It’s a really important milestone as it will allow us to scale more easily as a company,” Paterson said. “We are now at the phase where we can build out the portfolio of IP.”
The agileOSC RC oscillator itself is based on a traditional architecture that allows the frequency to be trimmed to remove the effects of process variation. It can also be configured as a free running clock (FRC) where an accurate frequency is not required. With a start-up time of typically 10µs, it has a frequency range of 20kHz to 100MHz with an accuracy of up to +5%. Power consumption is typically around 100µA at 10MHz.