First silicon of a complex experimental chip designed at Bar-Ilan University has demonstrated the pairing of hardwired DSP intellectual property with modifiable instruction-set extensions deployed on an embedded FPGA core.
The demonstration coupled Flex Logix’s EFLX embedded FPGA IP to a CEVA X2 DSP instruction extension interface as part of a project conducted by Bar-Ilan University SoC Lab, a member of the HiPer Consortium backed by the Israeli Innovation Authority (IIA), to build a high-integration multicore ASIC called SOC2, which has been fabbed by TSMC on a 16nm process. According to Andy Jaros, vice president of sales, marketing and solutions architecture, an additional EFLX instance was deployed on the system bus to allow for programmable SoC-management circuitry.
“The ability to add custom instructions to minimize power and maximize performance efficiency of embedded processors has been around for decades,” said Jaros. “The ISA extension capability works great for targeted applications, but it can be a costly solution when the application changes or new use cases need different instructions requiring a new chip to be developed. By working with CEVA and the HiPer Consortium, the SOC2 proves that reconfigurable computing is here with a DSP instruction set architecture that can be adapted to different workloads with custom hard-wired instructions that can be changed at any time in the future.”
Erez Bar-Niv, Ceva’s CTO added, “The SOC2 contains two processing clusters, each containing two X2 DSP cores and EFLX eFPGA for programming and executing DSP instructions extensions, connected using the CEVA-Xtend mechanism.”