App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
Imagination Technologies has launched a new generation of GPU IP aimed at multitasking compute acceleration.
GlobalFoundries and TSMC have called off their legal battle with a wide-ranging patent cross-licensing deal.
October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
Mentor is active across the program at Arm TechCon with a range of conference and booth talks, demonstrations and presentations.
Accellera's security assurance working group has set out some of its plans in a white paper.
Ceva has employed a more extensive form of weight compression in its latest generation of DNN processor cores.
IP core focuses on avodiing memory access bottlenecks during processing of complex machine-learning and artificial-intelligence algortihms.
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