The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
Registration has opened for the first ES Design West exhibition, which takes place alongside Semicon West in San Francisco in July.
The Design Automation Conference (DAC) has kicked off free registration for the exhibit floor at early June's Las Vegas event.
5G has given Beijing a development template to use across its Made in China 2025 program.
Graphcore has licensed IP from Belgium-based Sofics to protect its Colossus GC2 processors from ESD.
Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?
UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.
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