IP

March 23, 2022

Nvidia open to chiplet standards

Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
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February 8, 2022

Arm aims for IPO as Nvidia calls off its bid

Nvidia has decided to give up on acquiring Arm from SoftBank. The IP provider will now aim for an IPO by the end of March 2023.
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December 6, 2021

Imperas pulls together tools for RISC-V verification

Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
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November 23, 2021

DAC 2021 Preview: Siemens EDA

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
November 8, 2021

Chiplets may have to prove themselves for secure operation

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
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November 5, 2021

UK consortium starts work on cryogenic CMOS

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
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November 4, 2021

Design management survey points to more tactical cloud EDA

Cloud computing is gaining ground in EDA but close to a third of organizations are planning to stay with on-premises computing for the foreseeable future, according to a survey commissioned by IC Manage.
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November 3, 2021

Python provides the link for speed checks at Sondrel

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
November 2, 2021

Glitch detection cores add to Agile portfolio

Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
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October 28, 2021

Emulation’s scheduling challenge

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
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