IP

June 5, 2019

Microsoft Azure aims to get inside SoCs with cloud security plan

Microsoft Azure aims to use royalty-free IP to build a more secure IoT and extend the reach of its cloud services.
Article  |  Tags: , , , , ,   |  Organizations:
June 4, 2019

The unknown unknowns of secure devices

Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.
May 28, 2019

Cadence expands Protium for rack-based prototyping

Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
May 21, 2019

Achronix deploys network on chip for faster FPGAs

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Article  |  Tags: , , , , , , , ,   |  Organizations:
May 20, 2019

DAC 2019 preview: Mentor

Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.
May 3, 2019

ES Design West outreach attracts launch participants

EDA and IP supporters of the new event see the goal of greater integration with the electronic systems supply chain as fundamental to their involvement.
April 24, 2019

May meeting to push for UVM analog extensions

Accellera is trying to standardize extensions to UVM for mixed-signal design.
Article  |  Tags: , ,   |  Organizations:
April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
Article  |  Tags: , , , , ,   |  Organizations: , ,
April 12, 2019

DesignWare gets automotive boost with GLOBALFOUNDRIES 22FDX SOI qualification

Synopsys and GLOBALFOUNDRIES are developing a portfolio of automotive IP for the chipmakerā€™s 22nm fully depleted silicon-on-insulator (22FDX) process.
Article  |  Tags: , , , ,
April 2, 2019

Catapult HLS integrates eFPGA IP for faster development

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
Article  |  Tags: , , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors