Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
IP
Agile Analog adds digital library for easier porting
Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Accellera attempts to standardize CDC data
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Open-source EDA grapples with the incentives issue
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Agile starts to build out analog portfolio with tool-based strategy
Agile Analog's oscillator IP sees the company focus on IP created with its own circuit creation and porting tool.
Primarius adds to library-development lineup
Primarius Technologies is making additions to its portfolio of library-design and verification tools at DAC next week.
SoC project uses eFPGA to extend DSP instructions
R&D multicore processor demonstrates programmable extensions for DSP.