Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
IP
Accellera attempts to standardize CDC data
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Open-source EDA grapples with the incentives issue
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Agile starts to build out analog portfolio with tool-based strategy
Agile Analog's oscillator IP sees the company focus on IP created with its own circuit creation and porting tool.
Primarius adds to library-development lineup
Primarius Technologies is making additions to its portfolio of library-design and verification tools at DAC next week.
SoC project uses eFPGA to extend DSP instructions
R&D multicore processor demonstrates programmable extensions for DSP.
Imagination brings in lower-cost access for accelerator IP
Imagination Technologies has dropped the requirement to take an upfront licence for some of its IP cores if customers join its Open Access program.
Saber models aim for ADI power chips
Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.
Nvidia open to chiplet standards
Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
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