EDA

June 15, 2017

Smart code editor adds SystemVerilog support

Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking
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June 14, 2017

DAC 2017 preview: Oski Technology

Oski Technology will offer a range of daily presentations at its DAC 2017 and useful technical advice in the main conference program.
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June 14, 2017

DAC 2017 preview: ESD Alliance

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
June 13, 2017

Verific buys rapid tool development platform

Verific has acquired the Invio custom-tool development environment developed by Invionics Software.
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June 8, 2017

DAC 2017 preview: OneSpin

Formal, AI and UVM form key parts of the OneSpin agenda for this year's Design Automation Conference.
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June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
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May 24, 2017

Austemper tools straddle the functional-safety flow

Austemper Design Systems has launched a portfolio of tools that span the development lifecycle of projects that need to demonstrate functional safety.
May 19, 2017

DAC to train on machine learning

DAC's traditional training day is expanding into the field of machine learning this year in Austin.
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May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
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