EDA

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.

Engineering consultancy pays undisclosed sum for IMGworks division.

The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.