Cadence Design Systems has updated its FastSpice simulation engine with the launch of the FX version, designed to improve the software’s handling of large memories and SoCs.
The FX engine runs on up to 32 processors and uses a number of techniques to improve its ability to split workloads across cores. On circuits provided by customers, some applications, such as a post-layout simulation of a flash memory distributed across eight cores saw a 3.8x reduction in simulation time; a transceiver, again across eight cores a reduction of 3.7x.
Jay Madiraju, product management director at Cadence, said the new engine is better at automatically partitioning designs for commonly used tasks. “It’s fully automated. Previous tools required some guidance. We’re not asking the user to do low-level tuning.”
Because of the many heuristics needed in FastSpice operations, the parallelism involved remains lower than is possible with a full Spice simulation. “Thirty two cores is very high in the FastSpice field,” said Madiraju. “Traditionally, it hasn’t scaled as fast as Spice because of the sequential nature of many of the algorithms. You can never make it as parallel as Spice.”
However, non-uniform circuits that cover a large number of transistors or where arrays need to be treated differently because of area effects do provide scope for distributed processing, which is where Cadence expects the bigger speedups.
The Spectre FX Simulator offers a number of facilities, including interactive debug, static and dynamic circuit checking, sweeps and Monte Carlo analyses. A further feature is the ability to save and restore at checkpoints to try alternatives without having to run a complete simulation from the start or just to break up simulation into manageable pieces.