EDA

Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.

Canadian startup Invionics has launched a development environment and packager intended to make it easier for users within chipmakers and design houses to build customized tools.

UK-based RAL Space has picked up an award from National Instruments for a system the organization built to test a pair of cameras ahead of being being deployed on the International Space Station to photograph the Earth from orbit.

Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.

The latest update to Mentor's market-leading PCB design suite aims to unify system definitions across multiple tools to reduce errors.

Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab