EDA

Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.

Unsettled by attacks on embedded devices such as the point-of-sale terminals used by retailers such as Target and the potential for hackers to target critical infrastructure, the industry focused squarely on security at this year’s Embedded World in Nürnberg, Germany.

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.

Express Logic has developed a tool to monitor the real-time resource requirements of multithreaded embedded systems that lets designers tune task priorities, stack usage and other factors for improved efficiency and memory usage.

The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (February 20)

New portfolio integrates and extends existing industrial embedded tools to meet the demands of Industry 4.0

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.

Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.