Cadence updates Xtensa with memory and power saving features

By Chris Edwards |  No Comments  |  Posted: January 14, 2015
Topics/Categories: Blog - Embedded, IP  |  Tags: , , ,  | Organizations:

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with extensions for power-saving caches and memory accesses.

The company said changes to the core design of the Xtensa 11 and LX6 can result in dynamic switching power savings in the logic sections of up to 25 per cent. For improved memory power consumption, it is now possible to power down portions of the cache by reducing the associativity.

When the processor is fully active, the cache may support, for example, a four-way associativity scheme. By reducing the cache in size and associativity to a single-way, direct-mapped during quiet periods, the cache power consumption can be reduced by 75 per cent.

Another memory change is support for prefetches into the data cache, which can reduce system-bus read operations by 23 per cent and which will speed up data-copying functions by a factor of six.

In addition, the company has made the support for very long instruction word (VLIW) processing more flexible by allowing the instructions to vary in length from 4 bytes to 16. Where parallelism is restricted, this can reduce code size and allow for smaller code and cache memories.

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