EDA

Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.

Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates

Cadence Design Systems has built a verification environment around its vManager software for ICs and systems that need to conform to the ISO 26262 safety standard.

Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android

DVCon Europe brings design and verification insights to Munich next week.

A demo at ARM TechCon showed one way malware could be foiled on systems that run software of uncertain provenance.

Carbon Design Systems has introduced a web portal to streamline the process of finding the most appropriate executable models for a system-level virtual prototype.

The Liberty library format has been extended to cope with the most common forms of on-chip variation analysis in use today on nanometer processes.

Does the internet of things (IoT) require a change in design techniques? A number of people involved in the EDA industry reckon it does.

Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.