ARM eases interconnect, debug, third-party IP integration for SoCs

By Luke Collins |  No Comments  |  Posted: June 3, 2015
Topics/Categories: Blog Topics  |  Tags: , , ,  | Organizations: ,

ARM is releasing tools, based on technology gained from its acquisition of Duolog Technologies last year, which will make it easier for SoC designers to configure and integrate SoC interconnect, as well as trace and debug infrastructure. The tools should also make the integration of third-party IP into these schemes easier.

CoreSight Creator offers a guided process through which users can configure CoreSight debug and trace system IP for their SoC. Once the configuration is complete, the tool will generate the necessary microarchitecture and RTL description to implement the facility in the design.

CoreLink Creator does a similar job for configuring ARM interconnect IP, up to and including the upcoming NIC-450, a development of the existing NIC-400 interconnect fabric. The NIC-450 interconnect fabric will enable the creation of a hierarchy or ‘network of  networks’ of NIC-400 interconnects, to enable clean partitioning across multiple power/voltage domains. ARM says that using CoreLink Creator to produce a NIC-450 interconnect scheme will mean deadlock-free operation.

The third part of this launch is Socrates DE, which includes a catalogue that enables users to choose and configure the major IP blocks for an SoC, guided by rules checks based on ARM architects’ experience. The tool can also take in RTL IP, from ARM or third parties, and provide it with an IP-XACT wrapper, by recognising and connecting any relevant bus structures on the candidate block, such as AXI and AHB, to the IP-XACT wrapper.

ARM's tools automate the integration of interconnect, debug and trace, as well as third-party IP blocks (Source: ARM)

Figure 1 ARM's tools automate the integration of interconnect, debug and trace, as well as third-party IP blocks (Source: ARM)

Once all the blocks have been chosen and configured, CoreSight Creator can analyse the IP-XACT descriptions of all the blocks and create a high-level specification of all the signals going into and out of the  debug subsystem. Next, the tool synthesises the microarchitecture of the trace and debug subsystem, including all its components and required interconnect.

CoreLink Creator does a similar job in terms of creating the systems interconnect for the SoC, based on its analysis of the system architecture defined by the user. Both tools output RTL specifications and test benches to be integrated into the overall SoC RTL flow.

Socrates DE and CoreSight Creator are available now. CoreLink Creator and CoreLink NIC-450 will be available for delivery in the second half of 2015.

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