DAC 2015: Mentor Graphics at the Design Automation Conference

By Paul Dempsey |  No Comments  |  Posted: June 5, 2015
Topics/Categories: Conferences, Blog - EDA, Embedded, IP, PCB  |  Tags:  | Organizations:

Today (June 5) is your last chance to pre-register for many of the technical events that Mentor Graphics (Booth #1432) will be running at next week’s Design Automation Conference in San Francisco. You can take your chance on the day, but seating is limited. The topics for those follow, but first here are some of the broader Mentor activities.

Main program highlights

First though, a few of the open highlights, and the first of these has to be the ‘Fireside Chat’ between Mentor Chairman and CEO Wally Rhines and our colleague from Semiwiki Daniel Nenni. This is part of the main program with admission to all attendees, including exhibition only. You can catch up on Wally’s latest thoughts on the business on Monday (June 8, 11.30am) in Booth #311.

Another main conference session we would point you at will feature Mentor verification expert Harry Foster going over some of the key trends from the 2014 Functional Verification study conducted by Wilson Research. Harry’s article here on aspects where smaller rather than larger designs face a greater respin risk is already one of the most popular we’ve published. Many of you will want to hear more about what that data said and you can do so on Tuesday (June 9, 3.30pm) in Booth #311, the Pavilion Theater.

Experts at the Mentor booth

Mentor will be running a series of open panels and technical sessions on its booth (#1432). It’s following the lead set by DAC and stripping all but one of these in at the same time each day, 4.00pm.


Monday’s (June 8, 4.00pm) panel, Meeting exploding demand throughout the ecosystem, features speakers from Samsung, eSilicon and UMC. It will look at the implications of combined demand for the latest nodes and the explosion in that for more mature ones being driven by the Internet of Things. How can companies get the most from their products as technology life cycles change? Michael Buehler-Garcia, senior director of marketing for Mentor’s Calibre products takes the chair.

Tuesday’s (June 9, 4.00pm) panel asks the question Emulation – Why so much talk? Speakers from AMD, Vista Ventures and STMicroelectronics will join verification consultant and Tech Design Forum contributor Lauro Rizzatti to look at why emulation’s use cases are expanding across the flow, from hardware into software verification, and increasingly leveraging techniques such as transaction-based emulation. It looks like Lauro’s got what he asked for.

Wednesday’s (June 10, 4.00pm) panel, The IC Design Waterfall: How advanced design techniques are now a requirement at established nodes, again finds Michael Buehler-Garcia in the chair. This time he is joined by experts from SMIC, ams and Semico Research to discuss how the need for complex integration at every node is making sign-off ever harder, and what can be done about it.

Technical sessions

Monday (June 8, 3.00pm NB) and Tuesday (June 9, 4.00pm) will feature a booth session on the use of Mentor’s Eldo circuit simulator for the development of smart power ICs robust enough to meet the demands of the automotive sector.

Expert insights

Beyond all those activities, Mentor’s registration-based sessions run the gamut and chiop and system design. Topics this year include (deep breath):

AMS/Custom IC Design

  • Accurate and Efficient Embedded SRAM Power Characterization
  • Accurate nm Circuit Verification and Device Noise Analysis of Analog/Mixed-Signal ICs
  • Pyxis IC Station for IoT Applications
  • Reliability Analysis of Analog-Centric ICs for Automotive Applications

Design and Functional Verification

  • Customer Case Studies Using Automated Formal and CDC Apps
  • Enterprise Verification: Productivity from Formal – Simulation – Emulation
  • EZ Verification with Questa VIP
  • Maximize your Bug-finding Productivity with the Visualizer Debug Environment
  • Proven Verification Performance with Questa and Mentor EVP
  • Veloce – the Technology Leader in Emulation

IC Design & Test

  • Calibre: We’ve Already Got You Covered for 10nm
  • Competing in Reliability Focused Growth Markets with Calibre PERC
  • Design Domain Controlled Chip, Package & Board Co-Optimization
  • DFM and Fill Update for Advanced Nodes
  • DRC-Clean Cell Design in 30 Minutes – Qualcomm’s Experience with Calibre RealTime
  • How to Banish Waiver Worry from your Design Flow
  • Meeting New Extraction Challenges at Advanced Nodes and Advanced Designs
  • Mentor RTL to GDS Digital Implementation for Best PPA at Advanced Nodes
  • Scalable Test Solutions for Giga-gate Designs
  • The Internet of Things (IoT) and Increased Design Complexity in Established Nodes

As noted, today is basically your last chance to check the list in full and pre-register online. You can do that by pointing your browser here to avoid disappointment on the day.



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