EDA

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.

Minima Processor is working on the first processor cores that will be customized to use its timing-control technology to push supply voltages into the near-threshold zone.

Will discuss how automotive OEMs and chip designers can use AI, deep learning, and convolutional neural networks to achieve better performance than traditional techniques.

Solido acquisition will also add further machine learning expertise to Mentor's capabilities.

Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.

Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.

Codasip has added a processor core aimed at low-energy IoT nodes to its growing portfolio of customizable designs based on the RISC-V architecture.