Codasip adds IoT core to RISC-V line

By Chris Edwards |  No Comments  |  Posted: August 21, 2017
Topics/Categories: Blog - IP  |  Tags: , ,  | Organizations:

Codasip has added a processor core aimed at low-energy IoT nodes to its growing portfolio of customizable designs based on the RISC-V architecture.

Karel Masarik, CEO and founder of Codasip, said: “This processor is perfect for IoT ASIC designers looking to move up from 8bit processors to 32bit processors. Like all members of the Codasip Bk family of processors, the Bk-1 is fully compliant with the RISC-V open standard, assuring customers that their embedded software is truly portable and their designs are not locked into a proprietary instruction set architecture such as ARM.”

In its basic configuration, the Bk-1 consumes 9000 gates and is able to run at up to 350 MHz in a 55nm process. The Bk-1 can be provided with an optional power management unit, JTAG debug controller, and bridges to the AMBA buses so it can be easily integrated into designs that are based around the ARM bus infrastructure.

Codasip provides their customers with high-level design tools that automatically profile the embedded SW and allow ASIC designers to tune the Bk-1 processor for a target application.

Pricing of the Bk-1 processor starts at $40,000, positioning it against the Cortex-M processors available in ARM’s DesignStart program. However, the Codasip Bk-1 license agreement has no royalties, which will translate into lower volume costs. Codasip claimed the lack of royalty will save $300,000–400,000 in additional costs compared with ARM, Andes, and Cortus cores.

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