EDA

Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.

High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.

UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.

The PCB and wire harness design specialist has posted an online blog with tips and advice on using and licensing its tools for home use.

The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.

Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.

Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..