Tessent Streaming Scan Network to shrink SoC test writing and runtimes
Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.
EDA
User2User sets virtual 2020 dates: US in November, Europe in December
The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
DVCon keynoters look to software for verification optimization ideas
Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.
Mentor and Arm collaborate on RTL verification reviews
Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.
Deliver RFIC reliability and performance through automation
Today's increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.
Aprisa team to be doubled after Mentor purchase
Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
Cloud access to emulator helps AI processor start-up prove design, win funding
Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.
Cadence uses machine learning to trim constrained-random runtimes
Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
How to handle PCB constraints for IoT designs
An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.
Open-RAN puts more focus on emulation in testing programs
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
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