EDA

Pulsic has adopted the freemium approach with a tool that gives designers of analog circuits previews of how they will be implemented on-chip.

Electrostatic discharge verification is becoming increasingly hard to achieve but automated pre-loaded checks can now help.

Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.

Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.

Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.

Mentor, a Siemens business, has rebranded as Siemens EDA, almost almost four years after the EDA company was acquired.

Aldec updates tools to add support for the latest release of the VHDL verification methodology.

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.