PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
EDA
Cadence pushes its FastSpice to 32 cores
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Understand how DO-254 defines verification for avionics
The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.
How MaxLinear cut physical verification time with in-design DRC
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
Sigasi editor provided free for open-source hardware developers
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.
Siemens extends Solido’s reach into IP validation with Fractal
Latest acquisition adds technologies to mitigate rising verification time and cost for third-party IP.
Hardware verification puts software first
Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
Siemens buys formal start-up OneSpin
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
Navigating the Siemens EDA portfolio
The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Siemens cloud tool streamlines DFM for PCBs
Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
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