FPGA prototyping

July 9, 2013

Xilinx tapes out for first of 20nm-generation FPGAs

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
April 1, 2013

DAC 2013 Preview I: Putting users first and marking 50 years

In the first of our weekly DAC 2013 previews, we discuss program highlights with general chair Yervant Zorian, including an expanded Designer Track, keynotes and golden jubilee celebrations.
March 19, 2013

SoC prototyping ascends the learning curve

Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.
March 13, 2013

On the way to the system of systems

Experts from Cadence and Synopsys talk about the implications for designers of the rise of ‘systems of systems’.
February 11, 2013

25 million gate prototyper arrives through collaboration

A team effort between three French companies has resulted in the launch of an FPGA prototyping system that is intended to provide emulation of designs with up to 25 million ASIC gates.
Article  |  Topics: Blog - EDA  |  Tags:   |  Organizations: ,
November 12, 2012

Synopsys FPGA prototyping launch puts pragmatism first

HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.
Article  |  Topics: Blog Topics, Blog - EDA, - Verification  |  Tags:   |  Organizations:
October 30, 2012

Tektronix aims to slash FPGA prototype debug time

Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.
Article  |  Topics: Blog Topics, Blog - EDA, - General, Verification  |  Tags:   |  Organizations: ,
October 8, 2012

Synopsys buys EVE and the death of dogma

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
May 16, 2012

Cadence joins the dots for verification

The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.
Article  |  Topics: Blog Topics  |  Tags: , ,   |  Organizations:

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