FD-SOI to get foundry push in ST deal

By Chris Edwards |  1 Comment  |  Posted: June 11, 2012
Topics/Categories: Blog Topics, Design to Silicon, Digital/analog implementation  |  Tags:  | Organizations: ,

When STMicroelectronics’ mobile-phone device subsidiary ST-Ericsson said it was going to make future devices on fully depleted silicon-on-insulator (FD-SOI) wafers, the open question was: where? That question has now been answered and the answer fills in another blank: where can other companies access FD-SOI?

ST now has the choice of running the process not only at its relatively low-capacity plant in Crolles, France but GlobalFoundries’ 28nm and 20nm-capable fabs following a deal with the foundry supplier. Not only that, but GlobalFoundries will be able to offer FD-SOI manufacturing to its other customers, a decision that significantly bolsters the FD-SOI ecosystem. ST is putting the know-how into getting FD-SOI on 28nm and below up and running but should also gain the benefit of having other foundry users exploit the process, increase volume and, in turn, push down the price of the specialized wafers that FD-SOI relies upon.

ST said in a statement: “The 28nm FD-SOI generation, currently in the industrialization phase, is scheduled to be available for prototyping by July 2012 and the next node, the 20nm FD-SOI generation, is currently under development and is scheduled to be ready for prototyping by Q3 2013.”

Philippe Magarshack, corporate vice president of design enablement and services, added: “Porting libraries and physical IPs from 28nm Bulk CMOS to 28nm FD-SOI is straightforward, and designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to bulk, due to the absence of the MOS-history effect.

“In addition, FD-SOI can be used for either extreme performance or very low leakage on the same silicon, by biasing dynamically the substrate of the circuit. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus bulk CMOS.”

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