Denser DRAM looks to flash for inspiration

By Chris Edwards |  No Comments  |  Posted: May 20, 2021
Topics/Categories: Blog - IP  |  Tags: , ,  | Organizations:

Unisantis Electronics Singapore used the recent IEEE International Memory Workshop to unveil a flash-flavored variant of the capacitor-less DRAM that promised to continue memory scaling but which has been plagued by issues such as noise.

The company says it can apply its vertical transistor structure to what it calls Dynamic Flash Memory (DFM). It is a volatile memory that behaves, for the most part, in a similar fashion to 1T DRAM but which adds an extra control line, used to erase blocks of cells, that makes it behave more like a flash memory. The vertical nanowire-like structure makes it possible to provide the word-, bit- and additional plate-line connections in a crosspoint architecture and a 4F2 cell.

Plate line connections are made below the word line in the crosspoint structure

Image Plate line connections are made below the word line in the crosspoint structure

The company claims one of the key advantages of the plate line is that it reduces the capacitive coupling between the write line and the floating body of the storage transistor that leads to high noise during read operations.

The company claims the design of the memory cell will reduce the power consumption caused by refreshing the contents of the cells on a regular basis. Using TCAD, the designers of the DFM memory believe it can improve density four-fold over conventional DRAM, which today has topped out at around 16Gbit.

The core transistor is based on the company’s surround gate transistor structure, which uses a vertical stack in place of planar or horizontal fins to form the core channel. This allows one or more gates to be wrapped around the outside of the channel.

Unisantis says it plans to work on partnerships with memory suppliers and foundries to further develop the technology.

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