Altera and ARM unite FPGA and processor debug

By Chris Edwards |  No Comments  |  Posted: December 12, 2012
Topics/Categories: Blog - Embedded  |  Tags: , , ,  | Organizations: ,

Altera has cut a deal with ARM to bring unified debug support to the FPGA fabric and Cortex-A9 processors inside the Cyclone SoC products, using a specialized version of ARM’s DS5 tool.

Chris Balough, senior director of product marketing for Altera, said the deal struck with ARM made it possible to provide the tool for use with the Cyclone SoC FPGAs for just under $1000 rather than the $6000 it at which tools such as DS5 normally retail.

“This collaboration has been underway for a bit more than a year. We believe that it’s the first FPGA-adapted embedded software development toolkit concentrated on debug and performance analysis,” Balough claimed. “It’s the first time that ARM has done a vendor-specific toolkit with the DS5.

Balough said the main aim was to overcome the problem of synchronizing debug between the custom parts of the FPGA and software running on the ARM processors.

“In a device with 4000 wires that connect the ARM processors and the FPGA, our expectation is that customers will want to implement a lot of memory-mapped peripherals in the FPGA. And you will expect the debug tools for that system to work together,” Balough said. “With separate FPGA and processor JTAG debuggers you would have no way to coordinate debug. Imagine the headache if we took tomorrow’s chip and gave it yesterday’s tools.

“With DS5, as you are changing your definition of the memory-map, that changes in real time how the memory map is presented to the debugger.”

Javier Orensanz, head of marketing for the system design division, said: “The first thing we did was remove one of the JTAG adapters out of the picture. It makes sense to just have a single debug probe.”

Altera implemented the Coresight debug logic along the interface between the FPGA fabric and the processor complex so that signals going in could be traced and used for breakpoints. By inserting trace and breakpoint modules into the FPGA section itself, customers’ own blocks can provide triggers and trace information that’s captured by the JTAG probe.

Blocks designed by Altera that are dropped into the FPGA using its Qsys have register views already defined so that they appear automatically in the Eclipse-based tool. “We provide an Eclipse plugin to edit custom register definitions,” Orensanz added.

The DS5 also provides power and performance analysis. Counters implemented in FPGA blocks can provide data to the tool so that users can determine the utilization profile of custom accelerators, for example, and find out where bottlenecks lie in the system architecture.

“You can see when certain processes have been active, correlated with performance counters from the system,” said Orensanz. “So you can see when the CPUs are active and whether threads are waiting or not as well as information such as level-one cache misses.

“For power consumption analysis you can connect the Streamline tool to the energy probe or National Instruments data-acquisition equipment. You can hook it to the power rails on the board and measure each of them individually.”

Although Altera’s first foray into combining hardwired processors and FPGA fabric – Excalibur – was not successful, a pent-up demand over the following decade for that type of integration appears to have built up. The rise of virtual prototyping technology has also helped customers determine how they could use the devices prior to seeing actual silicon.

“We’ve a dozen customer commits for this device even though we have only just started sampling. We’ve been quite surprised at the level of market demand for this device. We’ve had the price negotiations and commitments to use the device even prior to using the silicon,” Balough said. “The feature set and the virtual-platform technology, that one-two combination has been very, very effective.”

Balough described a couple of customer calls in China that demonstrated why products like Cyclone SoC have better odds of succeeding than previous attempts to do this sort of integration.

“We visited a company in China doing power distribution. We were able to estimate at least a 50 per cent saving through integration. The next day we visited a well-known CNC manufacturer. They had an ARM processor, FPGA and DSP. Just through a block diagram we could estimate that we would save them around 50 per cent.”

One problem with Excalibur was that if customers did not like Altera’s choice of processor, that was enough to rule it out of a design. Times have changed.

“A lot of systems we look at do not have the ARM architecture today and yet that has not been an issue so far,” Balough claimed. “There used to be much more fragmentation around the instruction set architecture. Now, ARM has either been chosen by people or they are considering it.”

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