Real Intent state machine debug focuses on core errors

By Chris Edwards |  No Comments  |  Posted: February 26, 2014
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

Real Intent has updated its Ascent Implied Intent Verification (IIV) tool with analysis functions that pinpoint important errors in finite state machines to reduce the time it takes to sift through error reports and added support for the 2009 revision of SystemVerilog.

Ascent IIV is designed to hunt for bugs in state machines automatically, looking for problems such as potential deadlock conditions and dead code. Recognizing that some errors in the state machine code can generate a large number of secondary issues that a tool like this can flag up, the new version will look for and highlight the root causes within the RTL. Selecting the error in the tool will trace back to the source RTL itself.

In tests at a customer the tool was able to reduce by more than a factor of ten the number of errors that engineers had to look at by sorting them into critical and secondary problems.

Lisa Piper, senior manager of technical marketing at Real Intent, said: “The enhanced FSM checks and associated debug of IIV mean designers can find more bugs automatically without the need for any test benches. IIV’s root cause analysis dramatically reduces debug time by focusing the effort on the real design problems, without being distracted by related secondary issues.

“The enhancements we made to our SystemVerilog 2009 language support and file processing make it easier for design teams to adopt it into their existing design flows,” Piper added.

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