Tech Design Forum
Briefing
state machine
state machine
February 26, 2014
Real Intent state machine debug focuses on core errors
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
Article | Topics:
Blog - EDA
| Tags:
deadlock
,
debug
,
FSM
,
state machine
| Organizations:
RealIntent
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