14nm/16nm

March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
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January 5, 2015

Cadence high-level synthesis changes deal with congestion

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
December 16, 2014

14nm/16nm finFETs debut at IEDM

The International Electron Device Meeting (IEDM) has once again provided a chance for the major chipmakers to go head-to-head with their latest processes - this time with finFETs.
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November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
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November 12, 2014

TSMC begins risk production of 16FF+

TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.
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October 20, 2014

IBM pays GlobalFoundries to take on chipmaking operation

GlobalFoundries is to acquire IBM's fabs in a deal that sees the server maker pay the foundry $1.5bn over five years and agree to exclusivity to 10nm.
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October 3, 2014

ARM tools take aim at finFET layout, timing issues

ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.
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August 19, 2014

Simulations point to better performance for Intel 14nm finFET

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
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July 15, 2014

Cadence targets finFETs with RC extraction speedup

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
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June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
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