TSMC begins risk production of 16FF+

By Chris Edwards |  No Comments  |  Posted: November 12, 2014
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.

“Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology,” said TSMC President and Co-CEO, Dr. Mark Liu. “We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals.”

According to TSMC, the 16FF+ process is on track to pass full reliability qualification later in November. Close to 60 customer designs are currently scheduled to tape out on the process by the end of 2015. Due to rapid progress in yield and performance, TSMC anticipates the volume ramp for 16FF+ will begin around July in 2015.

Companies such as Avago, Freescale, LG Electronics, MediaTek, nVidia, Renesas, and Xilinx are among early users of the foundry’s 16nm finFET processes.

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