ARM tools take aim at finFET layout, timing issues

By Chris Edwards |  No Comments  |  Posted: October 3, 2014
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , , , ,  | Organizations:

ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company’s physical libraries.

By realigning the power network on finFET processes to better match the layout of standard-cell tracks, Artisan Power Grid Architect improved the density of a processor-based test design by 20 per cent. The Signoff Architect uses information from the ARM physical libraries to reduce the amount of margin that needs to be applied during variation-aware timing analysis.

Ron Moore, vice president of marketing of the physical design group, said: “This capability came out because our guys were trying to implement the [ARM IP] cores. And they said ‘power routing [with finFETs] is really hard’. It can cause all kinds of area explosion.”

From poly to fin count

The issue for power grids is that the poly pitch is no longer the determining factor for routing power down to the standard-cell rails. “It’s the number of fins,” said Moore.

The need for dummy fins in today’s finFET processes as well as the requirement for multi-fin devices within real-word cells made it unattractive to take traditional standard cell design techniques over into the finFET world. Pin-access problems with double-patterning restrictions on routing have caused an additional set of headaches. Coloring rules for double patterning also affect the layout of the power and ground rails.

Ideally, the rails would be the same width as signal traces to allow them to be colored alternately on 14nm and 16nm processes. Early research found that these thin rails would be inadequate for more power-hungry cells. But thicker rails impose constraints on the layout because the coloring rules tend to force a wider spacing to be used.

The physical designers decided the best approach to deal with finFET constraints was to develop libraries with fractional track counts – 7.5 and 10.5 – rather than traditional 8- and 12-track topologies. These fit the requirements for three- and four-fin devices reasonably well and, more importantly allow ‘half fins’ from adjacent cells to butt up against each other, a technique that saves space overall. To allow cells to sit as close to each other as possible but provide routing flexibility and support coloring rules, they can flip left-right and top-bottom, Moore said.

Track blocking

The result of the cell-design changes is a situation where odd and even numbers of tracks alternate rather than the traditional highly regular layouts of pre-finFET processes. Although it is possible to distribute power on metal-layer three (M3) using a regular layout, this causes problems for signal routing and, in turn, chip density. An M3 power track no longer necessarily aligns well with the cells underneath.

“Even if it is off by just 1nm you can block an entire cell routing track,” said Leah Schuth, manager technology marketing in the ARM physical design group. “Partners risk getting utilization below 60 per cent simply down to suboptimal power grid insertion.”

In principle, the problem can be addressed by taking note of the cell layouts. But the Artisan tool “avoids the designers having to study these very complex rules”, Schuth said. The tool slots in during the floorplanning phase, providing data for the layout tools.

“There is an interactive part of the tool,” said Moore. “The designers will get to power-grid placement. “The designers will get to power-grid placement and it will ask them questions that will detect their topology.”

Timing improvements

ARM developed the Signoff Architect tool to help the stage-based form of OCV analysis that TSMC recommends for advanced processes. Using analyses carried out by ARM of its own cells and their behavior under different design conditions, the tool provides data to the timing analyzer that goes further than the basic derate values provided by the foundry.

“Because we are part of the implementation we can be design specific,” Moore said. “If you derate every stage at a standard 8 per cent or whatever the value is, the compounding at the end of a long path is pretty phenomenal.”

Schuth said: “We are removing a lot of the pessimism and over-margining that we have been doing in our designs.”

Moore said the tool may be superseded by changes to standard EDA tools once the recently announced Liberty Variation Format (LVF) becomes supported. “It has not yet gone through standardization which is why we have to have our own utility for our architecture-specific data.

“We have been a proponent of the Liberty format. We were one of the key customers who proposed it to Synopsys. When it gets adopted, this tool may be obsoleted. But right now [conventional OCV derating] is a productivity inhibitor for our customers and we are going to do something about it,” Moore said.

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