Cadence targets finFETs with RC extraction speedup

By Chris Edwards |  No Comments  |  Posted: July 15, 2014
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations: ,

Cadence Design Systems has launched the latest of its verification tools for IC implementation to receive a reworking for better performance across a cluster of multicore servers or workstations. Joining Tempus and Voltus, Quantus QRC Extraction Solution introduces a new parasitic-extraction algorithm for the company designed to cope with finFET-based processes and intended to allow the analysis of RC parasitics effects to start earlier in the flow.

“We have greatly improved the performance and throughput for this product,” claimed KT Moore, senior group director of Cadence’s digital and signoff group. “We are up to five times faster than the previous solution and over competitors. One key piece of this is the scalability. We like being scalable over multiple machines and our scalability is predictable.”

Moore said the tool has been certified by TSMC for its 16nm finFET process. “Having their endorsement is key,” he added. “A lot of their customers are moving to 16nm.”

Updated parasitic extraction algorithm

For the Quantus tool, Cadence has adopted a random-walk algorithm for its 3D field solver to model capacitance, a problem that is greatly complicated by the finFET’s shape and the way that local interconnect wraps around the transistor. The algorithm offers accuracy for these structures as well as being faster than its predecessor, Moore said.

The average five-fold speedup is based on the ability to run an extraction across an increased number of machines.

In general, the biggest improvements in speed come when running multiple corners on the same segment of the chip, as this allows a greater distribution of the workload. “If you were only extracting three or four corners previously because of the speed but you really wanted to extract ten, now you have that opportunity to do it in a reasonable amount of time,” Moore said.

“Just having performance gives you some benefits but not the maximum. With Quantus you can accelerate when you start doing signoff – the idea is in-design convergence. Both Tempus [for timing signoff] and Voltus [for power-grid signoff] rely on having some form of extracted netlist,” Moore explained. “Using Quantus, you can pull these analyses earlier into the flow.”

Moore used the example of interconnect analysis prior to detailed layout using access to Quantus from within the company’s Encounter environment. “Say I’ve worked out my floorplan but I have no clue whether the clocking strategy will work. I can insert and route the clock tree to the floorplanned blocks and then run extraction using QRC from within Encounter to figure out where things are at in terms of setup and hold. Using that form of in-design closure maximizes performance.”

For custom design, the Quantus analysis can be performed either interactively from within the Virtuoso cockpit to help guide layout decisions and avoid problematic structures or to check a completed circuit design to ensure that it is within tolerance.

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