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December 11, 2012
Semiconductor roadmap gets fuzzier at IEDM
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
Article | Topics:
Conferences
,
Design to Silicon
,
Blog - EDA
| Tags:
10nm
,
14nm
,
22nm
,
3D-IC
,
3DIC
,
device architecture
,
double patterning
,
FD-SOI
,
finFET
,
IEDM 2012
,
IMEC
,
lithography
,
more than Moore
,
substrate stress
,
tunnel FET
| Organizations:
IBM
,
IEDM
,
Intel
March 15, 2012
CPTF notebook: From restricted to ‘proscriptive’ design rules
Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
Article | Topics:
Blog Topics
,
Conferences
,
Design to Silicon
| Tags:
10nm
,
14nm
,
CPTF
,
design rules
,
EUV
,
lithography
,
manufacturing
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