DVCon USA 2019 preview: SmartDV
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Author Archives: TDF Staff
DVCon USA 2019 preview: Mentor
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
Taking an IoT edge design from proof-of-concept to prototype
A new paper describes a case study for a pressure-sensing IoT application based on the ARM DesignStart platform and Mentor IoT tool flow.
Safety and test IP heads for automotive AI applications
Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
Synopsys gets big-chip signoff boost from Innovium
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Closing code coverage with a hardware-aware HLS-to-RTL flow
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Synopsys announces DDR5 and LPDDR5 interface IP
Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
Mentor extends Tessent for debug and automotive pattern generation
As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.