Author Archives: TDF Staff

July 30, 2018

Synopsys catalogues AI IP

The rapid growth of interest in machine learning and artificial intelligence has prompted Synopsys to bring all its AI IP together in a microsite and brochure.
Article  |  Topics: Blog - IP, - Product  |  Tags: ,   |  Organizations:
June 21, 2018

DAC 2018 preview: Real Intent

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
June 21, 2018

DAC 2018 preview: Breker Verification Systems

The portable stimulus pioneer will demonstrate how the technology and standard have been leveraged for its new Trek5 release.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: , ,   |  Organizations:
June 20, 2018

DAC 2018 preview: Mentor

Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
June 20, 2018

DAC 2018 preview: Austemper Design Systems

Functional safety specialist will demonstrate extensions to its own suite and co-host demos highlighting its collaboration with OneSpin Solutions.
June 19, 2018

DAC 2018 preview: ESD Alliance

The Electronic System Design Alliance will discuss its recent decision to join SEMI and highlight DAC's new Infrastructure Alley.
Article  |  Topics: Conferences, Blog - EDA, - General  |  Tags: , , ,   |  Organizations:
June 19, 2018

DAC 2018 preview: Baum

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.
Article  |  Topics: Digital/analog implementation, Blog - EDA, - RTL  |  Tags: , , ,   |  Organizations:
June 18, 2018

DAC 2018 preview: Verific

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
May 24, 2018

Case study demonstrates 59% extra power savings for HPC

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
Article  |  Topics: Digital/analog implementation, Blog - EDA, - HPC, RTL  |  Tags: , ,   |  Organizations: ,
May 2, 2018

User2User Silicon Valley rolls out later this month

Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.