Synopsys announces DDR5 and LPDDR5 interface IP
Synopsys has introduced DesignWare memory interface IP blocks for accessing the upcoming DDR5 and LPDDR5 SDRAMs.
The DesignWare DDR5 IP, operating at up to 4800Mbit/s data rates, can interface with multiple DIMMs per channel of up to 80bit wide. Synopsys is targeting artificial intelligence and data centre SoCs as key application areas for the interface IP.
Dermot O’Driscoll, vice president of product solutions, infrastructure line of business, Arm, said: “We’re working to maximize the performance of Arm Neoverse designs for infrastructure and cloud by optimizing Synopsys’ DDR5 and LPDDR5 IP together with “Zeus” and future CPUs.”
The LPDDR5 IP, running at up to 6400Mbit/s, has a dual-channel memory interface option that shares circuitry between independent channels, saving die area and power – useful for mobile and automotive SoCs. Both of the new IP blocks have several low-power states with short exit latencies, and multiple pre-trained states to enable dynamic frequency changes. The DDR5 and LPDDR5 controller and PHY work together over the DFI 5.0 interface, providing a complete memory interface IP solution for high-bandwidth, low-power SoC designs.
The DesignWare DDR5 and LPDDR5 IP solutions support DDR and LPDDR features including:
- Firmware-based training using an embedded calibration processor in the PHY. This optimizes memory training at boot time, to ensure the greatest data reliability and margin at the system level. It also allows fast updates to the training algorithms without needing hardware updates.
- Decision feedback equalization in the input receivers reduces the impact of inter-symbol interference, to improve signal integrity.
- Reliability, availability, and serviceability features including inline or sideband error-correcting codes, parity, and data cyclic redundancy checks, reduce system downtime.
Synopsys has extensive experience in hardening PHY IP onto many different processes, including the management of signal and power integrity issues, which should make implementing its DDR5 and LPDDR5 blocks faster and more straightforward.
Synopsys has also developed verification IP for DDR5 and LPDDR5, which includes randomised configuration and runtime selection, comprehensive coverage, a verification plan, and protocol checks.
Ryan Baxter, director of cloud and verticals at memory makers Micron, said: “The combination of Micron’s DRAM devices and Synopsys’ memory interface IP blocks solutions enables mutual customers to get a jump-start on their next-generation SoCs for emerging applications in AI, data centre, mobile, and automotive that require faster DRAM and new memory interfaces.”
Sunny Khang, vice president, head of DRAM product planning at SK hynix. “Our ongoing collaboration with Synopsys for testing, compatibility, and interoperability of Synopsys’ DesignWare LPDDR5 IP with SK hynix’ LPDDR5 device will enable our mutual customers to achieve their aggressive power, performance, and area targets.”
The VC Verification IP for DDR5 and LPDDR5 is available now.
The DesignWare DDR5 PHY and LPDDR5 PHY should be available in Q1 of 2019.
The DesignWare DDR5 Controller and LPDDR5 Controller should be available in Q2 of 2019.
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