Synopsys gets big-chip signoff boost from Innovium

By TDF Staff |  No Comments  |  Posted: January 21, 2019
Topics/Categories: Case Study, Verification  |  Tags: ,

Data-centre networking chip company Innovium has adopted the Synopsys IC Validator tool for physical signoff.

Innovium used IC Validator to do the physical verification for its 12.8Tbit/s throughput TERALYNX switch, exploiting the tool’s distributed processing support to share the work across more than 250 CPU cores. the tool was then able to do full-chip design rule checking (DRC) and layout-versus-schematic (LVS) signoff on TSMC’s 16nm finFET process in a day.

“Physical verification is on the critical path to our tapeout. Early physical verification closure is essential to ensure that design schedules are met,” said Keith Ring, vice president of technology, Innovium. “IC Validator performance enabled us to complete full-chip DRC and LVS signoff within a day for our flagship network switch design.”

IC Validator, part of Synopsys’ Fusion Design Platform, is a physical verification tool suite that handles issues tasks such as DRC, LVS, programmable electrical rule checks, dummy metal fill, and design-for-manufacturabilty improvements. The tool has been designed to get the best performance out of mainstream hardware, using memory-aware load scheduling and balancing, multi-threading and distributed processing strategies  to enable jobs to be shared over more than one thousand CPUs.

“Designers are challenged to close physical verification within schedule because of the increasing manufacturing complexity at advanced technology nodes,” said Christen Decoin, senior director of business development, Design Group at Synopsys. “Through high performance, scalability, and readily available optimized runsets from all major foundries, IC Validator is providing designers with the fastest path to production silicon.”

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