AI’s design speedups, with and without machine learning
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Author Archives: Chris Edwards
Xilinx retools Versal for high-end edge AI
Xilinx has reworked its Versal FPGA for edge-AI applications.
TSMC spins outs processes for automotive and RF
TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
IEDM looks for papers across 2D devices to 3DICs
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
Three libraries tune speed and density on TSMC’s 3nm process
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Arm rolls clickthrough license scheme into Flexible Access
Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
Cadence pushes its FastSpice to 32 cores
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Denser DRAM looks to flash for inspiration
Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
Sigasi editor provided free for open-source hardware developers
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.
Alternative scaling approaches form VLSI 2021 technology highlights
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.