DAC and RISC-V move in together at Moscone in December
DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.
Author Archives: Chris Edwards
ST makes its first 200mm SiC wafers
STMicroelectronics has made its first silicon carbide wafers that can be run on a 200mm line.
Cadence uses reinforcement learning to tune flow
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Arm shows off biggest flex processor so far
Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
Chiplet design raises big questions
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Chiplets to need digital twins for reliability
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Standard arrives for thermal simulation data
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Samsung moves further into 3D for denser flash
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Imec cuts transistor gap to less than 20nm with forksheets
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.