Standard arrives for thermal simulation data
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Author Archives: Chris Edwards
Samsung moves further into 3D for denser flash
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Imec cuts transistor gap to less than 20nm with forksheets
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
AI’s design speedups, with and without machine learning
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Xilinx retools Versal for high-end edge AI
Xilinx has reworked its Versal FPGA for edge-AI applications.
TSMC spins outs processes for automotive and RF
TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
IEDM looks for papers across 2D devices to 3DICs
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
Three libraries tune speed and density on TSMC’s 3nm process
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Arm rolls clickthrough license scheme into Flexible Access
Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
Cadence pushes its FastSpice to 32 cores
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.