deadlock


May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
September 10, 2015

Debug monitors look for deadlock

UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Article  |  Topics: Blog - Embedded  |  Tags: , ,   |  Organizations:
June 9, 2014

Applications won’t find all the bugs, but they have their uses

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
May 28, 2014

On-chip interconnect startup uses network theory to sidestep deadlocks

NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
February 26, 2014

Real Intent state machine debug focuses on core errors

Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
October 17, 2012

Mentor extends Questa with formal coverage checks

New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors